1. Field of the Invention
The present invention relates to a video signal processing apparatus that processes an input video signal to display at high quality on a display device, the input video signal being a telecine-converted video signal generated by a conversion system, such as the 2-3 pulldown conversion system, from a film.
2. Description of the Related Background Art
Video signals of a standard television format, such as the NTSC format, often include video signals based on films. A film is made of 24 frames per second. A video signal of the standard television format is made of 30 frames per second, and is an interlaced scan video signal having two fields for each frame. Since the number of frames per second differs between a video signal and a film, each frame of the film is usually telecine-converted by the 2-3 pulldown conversion system to obtain a video signal of the standard television format.
In the 2-3 pulldown conversion system, the first and the second field of the first frame of a video signal are produced from the first film frame, the first and the second field of a second frame and a first field of a third frame of the video signal are produced from the second film frame, and the second field of the third frame and the first field of a fourth frame of the video signal are produced from the third film frame. The following frames are converted similarly, so that two fields, three fields, two fields, three fields, etc. of the video signal are respectively produced from each consecutive film frame.
Thus, two film frames correspond to five frames of a standard television format video signal, and each film frame is alternately converted into a video signal of two fields and a video signal of three fields.
However, when a video based on the interlaced scan video signal which is telecine-converted is displayed on a display device, such as a PDP, then, for example, the third frame of the consecutive frames of the video signal is combined from images of the second and the third frames of the film. Therefore, there was a problem that the image quality is poorer than that of an original film.
In order to solve the problem, the applicant for this application has proposed a video signal processing apparatus that improves the display quality for telecine-converted images. As shown in FIG. 1, the video signal processing apparatus includes a 2-3 period detection circuit 1, a progressive scan conversion circuit 2, a selector switch 3, memories 4 and 5, a selector switch 6, a memory control circuit 7, and a conversion control circuit 8. The 2-3 period detection circuit 1 determines whether an input video signal is a signal portion of two fields or a signal portion of three fields per film frame. In response to a detection signal from the 2-3 period detection circuit 1, the progressive scan conversion circuit 2 converts the video signal into a video signal of a progressive line scan. For signal portions corresponding to two fields, the video signal of the two fields is temporarily stored and then alternately output for each field. For signal portions corresponding to three fields, the video signal of the first two fields is temporarily stored and then alternately output for each field. That is, if the 2-3 period detection circuit 1 detects a still picture field that is the same in two consecutive frames, then that still picture field is ignored. The selector switch 3 relays the output video signal of the progressive scan conversion circuit 2 to the memory 4 or 5. The memory control circuit 7 controls writing into the memories 4 and 5 and reading from the memories 4 and 5 for the video signal. The selector switch 6 outputs the video signal selectively read out from the memory 4 or 5. The conversion control circuit 8 controls timing for the switching of the selector switches 3 and 6 as well as the writing and reading with the memory control circuit 7.
In the video signal processing apparatus with the above configuration, assuming that the input video signal is a video signal that has been telecine-converted by 2-3 pulldown, then the video signal is converted into a sequence of fields as shown in FIG. 2B corresponding to film frames A, B, C, D and so on, as shown in FIG. 2A. The length of each film frame is 1/24 second, whereas the length of each field is 1/60 second.
The progressive scan conversion circuit 2 converts the telecine-converted video signal into a progressive line-scan video signal, so that it generates a video signal portion VA for one screen, as shown in FIG. 2C, by obtaining a video signal portion line by line in alternation from the first field A1 and the second field A2 of the first frame in FIG. 2B. A video signal portion VB for one screen is generated by obtaining a video signal portion line by line in alternation from the first field B1 and the second field B2 of the second frame in FIG. 2B. Subsequently, video signal portions VC and VD are generated in a similar manner. The length of each of these video signal portions VA, VB, VC and VD is 1/30 second.
The memory control circuit 7 writes the video signal that is output by the progressive scan conversion circuit 2 via the selector switch 3 in alternation into the memories 4 and 5. The switching of the selector switch 3 is controlled by the conversion control circuit 8. The writing is performed at 24 Hz by thinning out the video signal. Assuming that the video signal portion VA is thinned out and written into the memory 4 as shown in FIG. 2D, then the video signal portion VB is subsequently thinned out and written into the memory 5 as shown in FIG. 2E. Then, the video signal portion VC is thinned out and written into the memory 4, and the video signal portion VD is thinned out and written into the memory 5.
The video signal portions VA, VB, VC and VD, which have been thinned out and written into the memories 4 and 5 as described above, are read out under the control of the memory control circuit 7. The reading is performed at 48 Hz, and is carried out twice in repetition for each of the memories 4 and 5. That is, as shown in FIG. 2F, the video signal portion VA is read out twice from the memory 4, and then, as shown in FIG. 2G, the video signal portion VB is read out twice from the memory 5. Similarly, the video signal portion VC is read out twice from the memory 4, and then the video signal portion VD is read out twice from the memory 5.
The video signal read out from the memories 4 and 5 is obtained via the selector switch 6. The selector switch 6 is switched by the conversion control circuit 8 to the side of the memory 4 when reading from the memory 4 and is switched to the side of the memory 5 when reading from the memory 5.
For the video signal portion VA read out from the memory 4 in the manner described above, an image based on that video signal portion VA is repeated twice and displayed for 1/48 second each time, as shown in FIG. 2H. Also for the video signal portions VB, VC and VD from the memories 4 and 5, an image based on each of those video signal portions is repeated twice and displayed for 1/48 second each time. That is, as in the film frames shown in FIG. 2A, the displayed video have one frame every 1/24 second.
It should be noted that each of the video signal portions VA, VB, VC and VD thinned out and stored in the memories 4 and 5 may also be repeatedly read out by n times at n 24 Hz, wherein n is an integer of 2 or greater. For example, if each of the video signal portions is repeatedly read out by three times at 72 Hz, then the video signal portion VA is repeatedly read out by three times from the memory 4 as shown in FIG. 2I, and then the video signal portion VB is repeatedly read out by three times in repetition from the memory 5 as shown in FIG. 2J. Similarly, the video signal portion VC is repeatedly read out by three times from the memory 4, and then the video signal portion VD is repeatedly read out by three times from the memory 5. For the video signal portion VA read out from the memory 4, an image based on that video signal portion VA is repeated by three time and displayed for 1/72 second each time, as shown in FIG. 2K. Also for each of the video signal portions VB, VC and VD from the memory 4 or 5, an image based on each of those video signal portions is repeated by three times and displayed for 1/72 second each time. That is, as in the film frames shown in FIG. 2A, the displayed video have one frame every 1/24 second.
However, when converting the frame rate of a telecine-converted video signal as shown in FIG. 2A to FIG. 2K, then an image of one film frame is displayed consecutively by a plurality of times (for example three times) for each 1/24 second. Thus, since displayed moving pictures are watched as if they moves jaggedly by the viewer, there is a problem of flickering.